Proceedings of The 17th Asian Test Symposium - November 24-27, 2008,Sapporo, Japan free download online

Title: Proceedings of The 17th Asian Test Symposium - November 24-27, 2008,Sapporo, Japan
Author(s): IEEE
Pages: 480
Publisher: IEEE
Publication date: 2008
Language: English
Format: PDF
ISBN-10: 0769533964
ISBN-13:
Description: Foreword Proceedings of the 17th Asian Test Symposium Welcome to the Seventeenth Asian Test Symposium (ATS08). Since 1992, ATS has been held every year in various Asian cities as the largest symposium that focuses on testing of integrated circuits and systems. Many researchers and engineers from all over the world have attended the past symposia and enjoyed discussions. This year ATS is being held in Sapporo, Japan. We have received 152 technical paper submissions from 19 countries and regions, including 37 from North and South America, 18 from Europe, 28 from Japan, 23 from Mainland China, 21 from Taiwan, 11 from India, 7 from Korea, 6 from other Asian countries and regions, and 1 from Africa. Each paper was sent to at least three reviewers for evaluation. The Program Committee meeting was held on July 4, 2008, at Campus Innovation Center Tokyo, and 62 papers were selected based on the reviewers rating and comments. The selected papers, which cover nearly all aspects of the key area of VLSI testing, were allocated into 20 technical sessions. We have also received 15 industry paper submissions and selected 12 of them to form an industry session. In addition to the technical and industry sessions, the ATS program includes two plenary sessions, two special sessions on analog production test, one panel session and two half-day tutorials. Two keynote addresses and two invited talks in the plenary sessions are given by Dr. Brian Stevens, Dr. Kunio Uchiyama, Dr. Brady Benware and Prof. Kunihiro Asada. Special session on analog production test is organized by Dr. Fidel Muradali and Dr. Jochen Rivoir. One panel session is organized by Dr. Anis Uzzaman. Two half-day tutorials are offered in cooperation with the Test Technology Test Education Program (TTEP) of IEEE Computer Society, Test Technology Technical Council (TTTC). One is on statistical screening methods by Prof. Adit Singh and the other is on delay testing by Dr. Srinivas Patil and Dr. Sreejit Chakravarty. Finally we would like to thank the reviewers, the Program Committee members, the Organizing Committee members, and the ATS Steering Committee members for their cooperation. And we also thank to all the authors who submitted their work to ATS 2008, and the program participants for their contribution at the symposium. Seiji Kajihara General Co-Chair Kyushu Institute of Technology Yasuo Sato General Co-Chair Hitachi, Ltd. Kazumi Hatayama Program Chair STARC Hiroshi Takahashi Program Vice-Chair Ehime University xii 17th Asian Test Symposium ATS 2008 Table of Contents Foreword................................................................................................................................................................xii ATS Steering Committee.............................................................................................................................xiii Organizing Committee..................................................................................................................................xiv Program Committee........................................................................................................................................xv Reviewers............................................................................................................................................................xvii TTTC Activities Board.................................................................................................................................xviii Tutorial 1................................................................................................................................................................xxi Tutorial 2..............................................................................................................................................................xxii ATS 2007 Best Paper Award....................................................................................................................xxiii Session 1: Plenary Session 1 Session 2: Plenary Session 2 Session 3A: Test Data & Response Compression Not All Xs are Bad for Scan Compression ..............................................................................................................7 Anshuman Chandra and Rohit Kapur Evaluation of Entropy Driven Compression Bounds on Industrial Designs ....................................................13 Srinivasulu Alampally, Jais Abraham, Rubin A. Parekhji, Rohit Kapur, and T.W. Williams Session 3B: Test Generation and Fault Simulation Untestable Fault Identification in Sequential Circuits Using Model-Checking ...............................................21 Jaan Raik, Hideo Fujiwara, Raimund Ubar, and Anna Krivenko A Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint ..........................................................................................................27 Ryoichi Inoue, Toshinori Hosokawa, and Hideo Fujiwara LIFTING: A Flexible Open-Source Fault Simulator ...........................................................................................35 Alberto Bosio and Giorgio Di Natale v Session 3C: RF Testing Digitally-Assisted Analog/RF Testing for Mixed-Signal SoCs .........................................................................43 Hsiu-Ming (Sherman) Chang, Min-Sheng (Mitchell) Lin, and Kwang-Ting (Tim) Cheng Low-Cost One-Port Approach for Testing Integrated RF Substrates ................................................................49 Abhilash Goyal and Madhavan Swaminathan Efficient Low-Cost Testing of Wireless OFDM Polar Transceiver Systems ...................................................55 Deuk Lee, Vishwanath Natarajan, Raj Senguttuvan, and Abhijit Chatterjee Session 4A: Test Compression and BIST Interconnect-Driven Layout-Aware Multiple Scan Tree Synthesis for Test Time, Data Compression and Routing Optimization ...........................................................................................63 Katherine Shu-Min Li and Jr-Yang Huang Sequential Circuit BIST Synthesis Using Spectrum and Noise from ATPG Patterns .......................................................................................................................................................................69 Nitin Yogi and Vishwani D. Agrawal A Novel BIST Scheme Using Test Vectors Applied by Circuit-under-Test Itself ............................................................................................................................................................................75 Jishun Kuang, Xiong Ouyang, and Zhiqiang You Session 4B: Test Generation for Physical Faults XPDF-ATPG: An Efficient Test Pattern Generation for Crosstalk-Induced Faults ..........................................................................................................................................................................83 Sunghoon Chun, Yongjoon Kim, Taejin Kim, Myung-Hoon Yang, and Sungho Kang A Multi-valued Algebra for Capacitance Induced Crosstalk Delay Faults .......................................................89 Arani Sinha, Sandeep K. Gupta, and Melvin A. Breuer Increasing Defect Coverage by Generating Test Vectors for Stuck-Open Faults ...........................................97 Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, and Yuzo Takamatsu Session 4C: Analog and Mixed-Signal Test Technique to Improve the Performance of Time-Interleaved A-D Converters with Mismatches of Non-linearity .........................................................................................................................105 Koji Asami, Hidetaka Suzuki, Hiroyuki Miyajima, Tetsuya Taura, and Haruo Kobayashi A Reduced Code Linearity Test Method for Pipelined A/D Converters ................................

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