Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture: December 1-5, 2007 free download online
Title: Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture: December 1-5, 2007 Author(s): IEEE Pages: 455 Publisher: IEEE Publication date: 2007 Language: English Format: PDF ISBN-10: 0769530478 ISBN-13: Description: Table of Contents
40th IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)
Message from the General Chairs ___________________________________________________ viii
Message from the Program Chairs ___________________________________________________ ix
Organizing Committee _________________________________________________________________ x
Reviewers _____________________________________________________________________________ xi
Session 1: Technology Issues
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0 _______________ 3
Naveen Muralimanohar, Rajeev Balasubramonian, and Norm Jouppi
Process Variation Tolerant 3T1D-Based Cache Architectures________________________________________ 15
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, and David Brooks
Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing _______________________________ 27
Radu Teodorescu, Jun Nakano, Abhishek Tiwari, and Josep Torrellas
Session 2A: Instruction Scheduling
Optimal versus Heuristic Global Code Scheduling ________________________________________________ 43
Sebastian Winkel
Global Multi-Threaded Instruction Scheduling ___________________________________________________ 56
Guilherme Ottoni and David August
Revisiting the Sequential Programming Model for Multi-Core _______________________________________ 69
Matthew Bridges, Neil Vachharajani, Yun Zhang, Thomas Jablin, and David August
Session 2B: Wear-Out Aware Architectures
Penelope: The NBTI-Aware Processor__________________________________________________________ 85
Jaume Abella, Xavier Vera, and Antonio Gonzalez
Software-Based Online Detection of Hardware Defects:
Mechanisms, Architectural Support, and Evaluation _______________________________________________ 97
Kypros Constantinides, Onur Mutlu, Todd Austin, and Valeria Bertacco
Self-calibrating Online Wearout Detection _____________________________________________________ 109
Jason Blome, Shuguang Feng, Shantanu Gupta, and Scott Mahlke
Session 3A: Memory
Implementing Signatures for Transactional Memory ______________________________________________ 123
Daniel Sanchez, Luke Yen, Mark D. Hill, and Karthikeyan Sankaralingam
Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in
Conventional and 3D Die-Stacked DRAMs_____________________________________________________ 134
Mrinmoy Ghosh and Hsien-Hsin S. Lee
v
Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors________________________________ 146
Onur Mutlu and Thomas Moscibroda
Session 3B: Networking and Security
Impact of Cache Coherence Protocols on the Processing of Network Traffic ___________________________ 161
Amit Kumar and Ram Huggahalli
Flattened Butterfly Topology for On-Chip Networks______________________________________________ 172
John Kim, James Balfour, and William Dally
Using Address Independent Seed Encryption and Bonsai Merkle Trees to
Make Secure Processors OS- and Performance-Friendly___________________________________________ 183
Brian Rogers, Siddhartha Chhabra, Milos Prvulovic, and Yan Solihin
Session 4A: Reliability
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding_______________________________ 197
Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Falsafi, and James Hoe
Argus: Low-Cost, Comprehensive Error Detection in Simple Cores __________________________________ 210
Albert Meixner, Michael E. Bauer, and Daniel Sorin
Leveraging 3D Technology for Improved Reliability _____________________________________________ 223
Niti Madan and Rajeev Balasubramonian
Effective Optimistic-Checker Tandem Core Design through Architectural Pruning ______________________ 236
Francisco Mesa-Martinez and Jose Renau
Session 4B: Simulation/Workload Analysis
FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators _______ 249
Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Patil, William Reinhart,
Darrel Eric Johnson, Jebediah Keefe, and Hari Angepat
Microarchitectural Design Space Exploration Using an Architecture-Centric Approach __________________ 262
Christophe Dubach, Timothy Jones, and Michael O’Boyle
Informed Microarchitecture Design Space Exploration Using Workload Dynamics______________________ 274
Chang-Burm Cho, Wangyuan Zhang, and Tao Li
Time Interpolation: So Many Metrics, So Few Registers___________________________________________ 286
Todd Mytkowicz, Peter F. Sweeney, Matthias Hauswirth, and Amer Diwan
Session 5: Prefetching and Snooping
Low-Cost Epoch-Based Correlation Prefetching for Commercial Applications _________________________ 301
Yuan Chou
A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy ______________________ 314
Jason Zebchuk, Elham Safi, and Andreas Moshovos
Uncorq: Unconstrained Snoop Request Delivery in Embedded-Ring Multiprocessors ____________________ 327
Karin Strauss, Xiaowei Shen, and Josep Torrellas
vi
Session 6: Parallelism and QoS in CMPs
A Framework for Providing Quality of Service in Chip Multi-Processors______________________________ 343
Fei Guo, Yan Solihin, Li Zhao, and Ravishankar Iyer
A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C Programs__________________ 356
William Thies, Vikram Chandrasekhar, and Saman Amarasinghe
Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures_________________________ 369
Michael Chu, Rajiv Ravindran, and Scott Mahlke
Session 7: Parallel Architectures
Composable Lightweight Processors __________________________________________________________ 381
Changkyu Kim, Simha Sethumadhavan, M.S. Govindan,
Nitya Ranganathan, Divya Gulati, Doug Burger, and Stephen W. Keckler
The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration______________ 394
Thomas Yeh, Petros Faloutsos, Milos Ercegovac, Sanjay Patel, and Glenn Reinman
Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow____________________________ 407
Wilson W.L. Fung, Ivan Sham, George Yuan, and Tor M. Aamodt
Session 8: Cache Replacement Policies
Scavenger: A New Last Level Cache Architecture with Global Block Priority__________________________ 421
Arkaprava Basu, Nevin K?rman, Meyrem K?rman,
Mainak Chaudhuri, and Jose Martinez
Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache_____________________________ 433
Stephen Hines, David Whalley, and Gary Tyson
Emulating Optimal Replacement with a Shepherd Cache __________________________________________ 445
Kaushik Rajan and Govindarajan Ramaswamy
Author Index ________________________________________________________________________ 455
* Publisher: IEEE Computer Society Press
* Number Of Pages: 455
* Publication Date: 2007-01
* ISBN-10 / ASIN: 0769530478
* ISBN-13 / EAN: 9780769530475
* Binding: Hardcover
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture: December 1-5, 2007 free download links:
Title: Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture: December 1-5, 2007